The ARINC 818 Gen 2 IP Core from Great River Technology is a high-performance, next-generation solution for implementing ARINC 818-compliant video interfaces in modern FPGA designs. Designed for advanced avionics displays and high-speed sensor applications, Gen 2 significantly expands bandwidth, integration flexibility, and built-in functionality.

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The Gen 2 core supports link rates up to 32X using 64b/66b encoding, enabling reliable transport of ultra-high-resolution and high-frame-rate video over ARINC 818. The core pairs with high-speed serial transceivers (e.g., Intel GX or AMD/Xilinx GT tiles) and can be configured for transmit-only, receive-only, or full duplex operation.

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To simplify system integration, the Gen 2 IP Core features AXI4-Stream and AXI4-Lite interfaces, allowing seamless connection to video pipelines, DMA engines, and control logic within the FPGA. An embedded video timing generator is included, supporting both Master mode—where the core controls video timing and queries pixel data—and Slave mode, where an external source supplies pixel data and timing.

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The core provides extensive compile-time configurability for link speed, line segmentation, synchronization methods, resolution, and pixel packing, along with support for additional pixel formats such as Bayer and YCbCr, making it ideal for high-speed imaging sensors and advanced display systems. Ancillary data can be set to default values or updated dynamically in real time via the register interface.

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Built-in test capabilities and enhanced error detection improve system observability, validation, and operational robustness—especially important for mission-critical avionics applications.

The ARINC 818 Gen 2 IP Core is delivered as encrypted VHDL. Great River Technology also offers an Airborne Atomic IP Core package that includes all required elements to support DO-254 certification.