The ARINC 818 Gen 4 IP Core from Great River Technology is a high-performance, next-generation solution for implementing ARINC 818-3 video interfaces in modern FPGA designs. Designed for advanced avionics displays and high-speed sensor applications, our Atomic IP Core significantly expands bandwidth, integration flexibility, and built-in functionality.

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The Gen 4 core supports link rates up to 24X using 64b/66b encoding, enabling reliable transport of ultra-high-resolution and high-frame-rate video over ARINC 818. The core pairs with high-speed serial transceivers (e.g., Intel GX or AMD/Xilinx GT tiles) and can be configured for transmit-only, receive-only, or full dual operation.

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An embedded video timing generator is included, supporting both Master mode—where the core controls video timing and queries pixel data—and Slave mode, where an external source supplies pixel data and timing.

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The core provides extensive compile-time configurability for link speed, line segmentation, synchronization methods, resolution, and pixel packing. It supports pixel packing such as RGB, YCbCr, or Mono, along with support for custom pixel formats, making it ideal for high-speed imaging sensors and advanced display systems. Ancillary data can be set to default values or updated dynamically in real time via the register interface.

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Built-in test capabilities and enhanced error detection improve system observability, validation, and operational robustness—especially important for mission-critical avionics applications.

The ARINC 818 Gen 4 IP Core is delivered as encrypted VHDL.