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ARINC 818 IP Core by Great River Technology provides an easy way to implement ARINC 818-compliant interfaces in many common FPGAs. The core pairs with the high-speed serial tiles of the FPGA (e.g., GX or GT tiles) to achieve ARINC 818 interfaces up to 10.0 Gbps. The core can be used for transmit only, receive only, or for transmit and receive applications.

The core has many flexible compile time settings allowing for various link speeds, line segmentations, and line synchronization methods. The core can be configured for various resolutions and pixel-packing methods. Transmitted Ancillary data can use default values (set at compile time) or data can be updated in real-time via register interface.

The ARINC 818 IP core is delivered as encrypted VHDL. GRT also offers an Airborne Atomic IP Core package with all elements to support DO-254 certification.

Currently, GRT offers the ARINC 818 IP Core for a broad range of Intel and Xilinx FPGAs.

GRT sells our IP core bundled with essential development tools in five different packages:

Encrypted IP Core Package

Receiver Development Package
Transmitter Development Package
Total Development Package
Airborne Package



The ARINC 818 Atomic IP Core is compile-time configurable to match the specific requirements of your ARINC 818 video format. Features and supported formats include:

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