GRT’s ARINC 818 Atomic transceiver core provides an easy way to implement ARINC 818 compliant interfaces in many common FPGAs. The core pairs with the high speed serial tiles of the FPGA (e.g., GX or GT tiles) to achieve ARINC 818 interfaces up to 8.5 Gbps. The core can be used for transmit only, receive only, or for transmit and receive applications.

The core has many flexible compile time settings allowing for various link speeds, line segmentations, and line synchronization methods. The core can be configured for various resolutions and pixel packing methods. Transmitted Ancillary data can use default values (set at compile time) or data can be updated in real time via register interface.

The Atomic IP core is delivered as encrypted VHDL. GRT also offers an Airborne Atomic IP Core package with all elements to support DO-254 certification.

Currently, GRT offers the IP Core for a broad range of Altera and Xilinx FPGAs.

GRT sells our IP core bundled with essential development tools in five different packages:

Encrypted IP Core
Receiver Development Package
Transmitter Development Package
Total Development Package
Airborne Package

IP CORE

USEFUL LINKS

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Features

• Available for most Xilinx and Altera FPGAs with Gigabit transceivers

• Supports all ARINC 818 Link speeds up to 8.5 Gbps

• Simple pixel bus interface

• Compile time configurable for ADVB video format (resolution, pixel type, etc.)

• Supports transmit only, receive only, or full transceiver instantiation

• Configurable for various line segmentations

• Supports line synchronous transmission

• Built-in pixel packing/unpacking

• Link status & detection outputs (CRC_error, SOF/EOF_det, etc.)

• Tx Object 0 Ancillary data real-time update

• Tx Object 0 default values compile-time settable

• Complete Object 0 Ancillary data recovery on Rx

• Airborne Certification package available